A phase locked loop is used to synchronize a phase of an output signal with the phase of an input signal. A typical phase locked loop includes a phase comparator, and voltage controlled oscillator. The phase comparator compares the phase of an output signal of the voltage controlled oscillator with the phase of the input signal. An output signal representing the phase difference is provided by the phase comparator. A delay locked loop differs from a phase locked loop in that in a voltage controlled delay (VCD) is used instead of a voltage controlled oscillator. Like the phase locked loop, the delay locked loop determines the phase difference between two signals and provides an output signal to adjust the delay of the VCD to "lock" the phase of the two signals. A problem with the conventional delay locked loop is that it can only phase lock two signals of the same frequency.
Two conventional circuits for providing a VCD in a delay locked loop are the shunt-capacitor type VCD and the starved-inverter VCD. In shunt-capacitor VCD, a capacitor with fixed capacitance is connected to the output of a CMOS inverter through a shunt transistor. By providing a gate-to-source voltage (VGS) to the shunt transistor, the transconductance of the shunt transistor can be increased which increases a capacitive loading at an output terminal of the CMOS inverter. By adjusting the voltage at the gate of shunt transistor, a predetermined delay can be introduced in the rise and fall times of the inverter output.
In the starved-inverter VCD, an N-channel transistor of a conventional two transistor inverter is connected in series with another N-channel transistor (known as a current-starving transistor). The gate of the current-starving transistor is controlled by a voltage which limits the amount of current that can be discharged through the inverter. The higher the VGS of the current-starving transistor, the faster the output terminal of the inverter can be reduced to ground potential.
In the shunt-capacitor VCD, the capacitive loading of the output is varied, while the inverter current stays fixed. In the starved-inverter VCD, the load capacitance remains fixed, while the inverter current is varied. These two designs work fine for most of VCD applications. However, both the shunt-capacitor VCD and the starved-inverter VCD require that the input signals of the VCD be CMOS (complementary metal-oxide semiconductor) level signals. If the input signals are relatively small signals, such as ECL (emitter-coupled logic) level signals, then they need to be converted to CMOS levels before being applied to the VCD. Also, the output signals of the VCD have to be reconverted to small signal, or ECL level signals. The level conversions, provide additional undesirable delay in the delay locked loop.
Another problem with the shunt-capacitor VCD is that it does not have a good maximum delay to minimum delay ratio. Thus, in order to increase the maximum delay, additional delay stages are needed. Adding delay stages to increase the maximum delay, also increases the minimum delay. The additional delay stages also increases layout area required for the VCD.
The starved-inverter VCD has a good maximum to minimum delay ratio. However, most of delay occurs when V.sub.GS is near the threshold voltage (V.sub.T) of the current-starving transistor. This means that the starved-inverter VCD is very sensitive to the noise.